Freescale Semiconductor /MK20DZ10 /I2S0 /CR

I2S Enable.

0 (0): I2S is disabled.

1 (1): I2S is enabled.

Transmit Enable.

0 (0): Transmit section disabled.

1 (1): Transmit section enabled.

Receive Enable.

0 (0): Receive section disabled.

1 (1): Receive section enabled.

Network Mode.

0 (0): Network mode not selected.

1 (1): Network mode selected.

Synchronous Mode.

0 (0): Asynchronous mode selected.

1 (1): Synchronous mode selected.

I2S Mode Select

0 (00): Normal mode

1 (01): I2S master mode

2 (10): I2S slave mode

3 (11): Normal mode

System Clock (Oversampling Clock) Enable.

0 (0): Network clock not output on SRCK port.

1 (1): Network clock output on SRCK port.

Two-Channel Operation Enable.

0 (0): Two-channel mode disabled.

1 (1): Two-channel mode enabled.

Clock Idle State.

0 (0): Clock idle state is `0’.

1 (1): Clock idle state is `1’.

Transmit Frame Clock Disable.

0 (0): Continue frame-sync/clock generation after current frame during which CR[TE] is cleared. This may be required when frame-sync and clocks are required from I2S, even when no data is to be received.

1 (1): Stop frame-sync/clock generation at next frame boundary. This will be effective also in case where transmitter is already disabled in current or previous frames.

Receive Frame Clock Disable.

0 (0): Continue frame-sync/clock generation after current frame during which CR[RE] is cleared. This may be required when Frame-sync and Clocks are required from I2S, even when no data is to be received.

1 (1): Stop frame-sync/clock generation at next frame boundary. This will be effective also in case where receiver is already disabled in current or previous frames.

no description available

0 (0): CR[TE] not latched with FS occurrence and used directly for transmitter enable/disable.

1 (1): CR[TE] latched with FS occurrence and latched-TE used for transmitter enable/disable.